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Features
* 16 Channel GPS Correlator
- 8192 Search Bins with GPS Acquisition Accelerator - Accuracy: 2.5m CEP (Stand-Alone, S/A off) - Time to First Fix: 34s (Cold Start) - Acquisition Sensitivity: -140 dBm - Tracking Sensitivity: -150 dBm Utilizes the ARM7TDMI(R) ARM(R) Thumb(R) Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Embedded ICE (In-circuit Emulator) 128 Kbyte Internal RAM 384 Kbyte Internal ROM with u-blox GPS Firmware Fully Programmable External Bus Interface (EBI) - Maximum External Address Space of 8 Mbytes - Up to 4 Chip Selects - Software Programmable 8-bit/16-bit External Data Bus 6-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 2 External Interrupts 32 User-programmable I/O Lines 1 USB Device Port - Universal Serial Bus (USB) V2.0 Full-speed Device Specification Compliant - Embedded USB V2.0 Full-speed Transceiver - Suspend/Resume Logic - Ping-pong Mode for Isochronous and Bulk Endpoints 2 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Master/Slave SPI Interface - 2 Dedicated Peripheral Data Controller (PDC) Channels - 8-bit to 16-bit Programmable Data Length - 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Power Management Controller (APMC) - Peripherals Can Be Deactivated Individually - Geared Master Clock to Reduce Power Consumption - Sleep State with Disabled Master Clock - Hibernate State with 32.768 kHz Master Clock Real Time Clock (RTC) 2.3V to 3.6V or 1.8V Supply Voltage Includes Power Supervisor 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance 1 Kbyte Battery Backup Memory 9 mm x 9 mm 100-pin BGA Package (LFBGA100)
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GPS Baseband Processor ATR0621 Summary Preliminary
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Electrostatic sensitive device. Observe precautions for handling.
Rev. 4890AS-GPS-09/05
Note: This is a summary document. A complete document is available under NDA. For more information, please contact your local Atmel sales office.
1. Description
The GPS baseband processor ATR0621 includes a 16-channel GPS correlator and is based on the ARM7TDMI(R) processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0621 has a USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 fullspeed device specification. The ATR0621 has a direct connection to off-chip memory, including Flash, through the External Bus Interface (EBI). The ATR0621 includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM. In order to be able to store configuration settings, connecting a serial EEPROM is supported. For customer-specific applications, a Software Development Kit is available. The ATR0621 is manufactured using the Atmel high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621 provides a highly-flexible and cost-effective solution for GPS applications.
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Figure 1-1. Block Diagram
XT_IN XT_OUT
GPS Correlators
Advanced Power Management Controller
Accelerator
SRAM
GPS
RTC
NSHDN NSLEEP
RF_ON CLK23
SIGLO0 SIGHI0
SDM Generator
P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 PIO2 PIO2 Controller APB SPI
Timer Counter
P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0
Special Function
USART2
P21/TXD2 PIO2 P22/RXD2
Advanced Interrupt Controller
USART1
P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED
P18/TXD1 P31/RXD1
USB Transceiver
Watchdog
P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1 EM_DA15 EM_DA0
USB_DP USB_DM
B R I D G E
USB ASB ARM7TDMI SRAM 128K ROM 384K PDC2
DBG_EN NTRST TDI TDO TCK TMS JTAG
Embedded ICE
Interface to Off-Chip Memory (EBI)
Power Supply Manager
VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN
NRESET
Reset Controller
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2. Architectural Overview
2.1 Description
The ATR0621 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0621 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. A bit can be set or reset by writing a "1" to the corresponding position at the appropriate address. Writing a "0" has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit-manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O (PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI(R) processor operates in little-endian mode on the ATR0621 GPS Baseband. The processor's internal architecture and the ARM (R) and Thumb (R) instruction sets are described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are described in detail in the ATR0621 full datasheet. The electrical and mechanical characteristics are also documented in the ATR0621 full datasheet. The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0621. Features of the ROM firmware are described in software documentation available from u-blox AG.
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3. Pin Configuration
3.1 Pinout
Pinout LFBGA100 (Top View)
Figure 3-1.
A B CDE F GH J K 10 9 8 7 6 5 4 3 2 1
Table 3-1.
Pin Name CLK23 DBG_EN EM_A1 EM_A2 EM_A3 EM_A4 EM_A5 EM_A6 EM_A7 EM_A8 EM_A9 EM_A10 EM_A11 EM_A12 EM_A13 EM_A14 EM_A15 EM_A16 EM_A17 Notes:
ATR0621
ATR0621 Pinout
LFBGA100 G9 H4 A6 A5 A4 A2 A3 B5 B4 B2 D4 C2 D6 D7 C3 C1 D5 C6 F8 Pin Type IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PD Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required.
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Table 3-1.
Pin Name EM_A18 EM_A19 EM_DA0 EM_DA1 EM_DA2 EM_DA3 EM_DA4 EM_DA5 EM_DA6 EM_DA7 EM_DA8 EM_DA9 EM_DA10 EM_DA11 EM_DA12 EM_DA13 EM_DA14 EM_DA15 GND GND GND GND LDOBAT_IN LDO_EN LDO_IN LDO_OUT NRESET NSHDN NSLEEP NTRST P0 P1 P2 P3 P4 P5 Notes:
ATR0621 Pinout (Continued)
LFBGA100 B3 C5 B6 B10 C7 C10 D10 E7 E9 B7 B8 A9 C8 B9 D8 C9 D9 E8 A1 A10 K1 K10 K8 H7 K7 H6 C4 G7 J6 K2 K9 G3 G4 H5 A7 B1 Pin Type OUT OUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN IN IN IN IN IN OUT I/O OUT OUT IN I/O I/O I/O I/O I/O I/O PD PD Configurable (PD) Configurable (PD) OH OH OH NANTSHORT GPSMODE0 BOOT_MODE NCS1 NCS0 NWE/NWR0 AGCOUT1 "0" NCS1 NCS0 NWE/NWR0 CLK32K "0" "0" "0" Open Drain PU PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required.
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Table 3-1.
Pin Name P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 RF_ON SIGHI0 SIGLO0 TCK TDI TDO TMS USB_DM USB_DP VBAT Notes:
ATR0621 Pinout (Continued)
LFBGA100 A8 D2 G2 J8 E4 H10 F3 G10 J5 K5 E1 J4 K4 F1 H2 F2 H8 H3 H1 D1 G8 E2 G1 E3 G5 H9 K6 F9 E10 J3 J2 K3 J1 F10 D3 J7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OUT OUT OUT IN IN OUT IN I/O I/O IN PU PU PU PU OH OH Configurable (PU) PU Configurable (PD) PD Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) Configurable (PU) Configurable (PU) PU Configurable (PU) Configurable (PU) Configurable (PU) Configurable (PU) Configurable (PU) OH Configurable (PU) PD PU PD Pull Resistor (Reset Value)(1) OH OH Firmware Label NOE/NRD NUB/NWR1 STATUSLED EXTINT0 EM_A0/NLB EM_A21 GPSMODE2 GPSMODE3 NAADET1 ANTON NEEPROM GPSMODE5 TXD1 GPSMODE6 TIMEPULSE TXD2 RXD2 GPSMODE7 GPSMODE8 NAADET0 GPSMODE10 GPSMODE11 EM_A20 GPSMODE12 AGCOUT0 RXD1 RXD1 RXD2 SCK MOSI MISO NSS SCK MOSI MISO NPCS0 NPCS1 NCS3 NPCS3 AGCOUT0 "0" EM_A20 MCLK_OUT "0" "0" "0" SIGLO1 SCK2 SCK2 TXD2 SIGHI1 SCK1 SCK1 TXD1 "0" "0" TIMEPULSE "0" NWD_OVF EXTINT1 "0" EXTINT0 EM_A0/NLB NCS2 NPCS2 "0" EM_A21 PIO Bank A NOE/NRD NUB/NWR1 "0" PIO Bank B "0" "0"
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required.
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Table 3-1.
Pin Name VBAT18 VDD18 VDD18 VDD18 VDDIO(2) VDD_USB XT_IN XT_OUT Notes:
(3)
ATR0621 Pinout (Continued)
LFBGA100 G6 E6 F7 F6 E5 F5 J9 J10 Pin Type OUT IN IN IN IN IN IN OUT Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required.
3.2
Signal Description
ATR0621 Signal Description
Name EM_A0 to EM_A21 NCS0 to NCS1 NCS2 to NCS3 NWR0 NWR1 EBI NRD NWE NOE NUB NLB BOOT_MODE TXD1-2 Function External Memory Address Bus Chip Select Chip Select Lower Byte Write Signal Upper Byte Write Signal Read Signal Write Enable Output Enable Upper Byte Select (16-bit SRAM) Lower Byte Select (16-bit SRAM) Boot Mode Input Transmit Data Output Receive Data Input External Synchronous Serial Clock USB Data (D+) USB Data (D-) Sleep Output Shutdown Output Oscillator Input Oscillator Output Type Output I/O Output Output Output Output Output Output Output Output Output Input Output Input I/O I/O I/O Output Output Output Input Output Active Level Comment - - Low Low Low Low Low Low Low Low Low - - - - - - - Low Low - - Interface to ATR0600 Interface to ATR0600 Connect to pin LDO_EN RTC oscillator RTC oscillator All valid after reset Internal pull-down resistor Output High in RESET state Output High in RESET state Output High in RESET state Output High in RESET state Output High in RESET state Output High in RESET state Output High in RESET state Output High in RESET state Output High in RESET state PIO-controlled after reset, internal pull-down resistor PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset
Table 3-2.
Module
EM_DA0 to EM_DA15 External Memory Data Bus
USART
RXD1-2 SCK1-2
USB APMC
USB_DP USB_DM RF_ON NSLEEP NSHDN XT_IN XT_OUT
RTC
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Table 3-2.
Module
ATR0621 Signal Description (Continued)
Name SCK MOSI Function SPI Clock Master Out Slave In Master In Slave Out Slave Select Slave Select Watchdog Timer Overflow Programmable I/O Port GPS Mode Digital IF Digital IF Digital IF Digital IF GPS synchronized time pulse Test Mode Select Test Data In Test Data Out Test Clock Test Reset Input Debug Enable Clock Input Master Clock Output Reset Input Type I/O I/O I/O I/O Output Output I/O Input Input Input Input Input Output Input Input Output Input Input Input Input Output I/O Power Power Power Power Power Power Power Out LDO In LDO Out LDO Enable Power Power Input Active Level Comment - - - Low Low - - - - - - - - - - - - Low - - - Low - - - - - - - - - - - Internal pull-up resistor Internal pull-down resistor Internal pull-down resistor Interface to ATR0600, Schmitt trigger input PIO-controlled after reset Open drain with internal pull-up resistor Core voltage 1.8V Backup power 1.8V Variable I/O voltage USB voltage 3.0V to 3.6V Ground 1.8V to 3.6V 1.95V to 3.6V 1.8V backup voltage 1.65V to 3.6V 1.8V core voltage, max. 100 mA PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset PIO-controlled after reset Interface to ATR0600 Interface to ATR0600 PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Internal pull-up resistor Internal pull-up resistor
SPI
MISO NSS/NPCS0 NPCS1-3
WD PIO
NWD_OVF P0-31 GPSMODE0-12 SIGHI1 SIGLO1 SIGHI2 SIGLO2 TIMEPULSE TMS TDI TDO TCK NTRST DBG_EN
GPS
JTAG/ICE
CLOCK
CLK23 MCLK_OUT
RESET
NRESET VDD18 VBAT18
POWER
VDDIO VDD_USB GND LDOBAT_IN
LDOBAT
VBAT VBAT18 LDO_IN
LDO18
LDO_OUT LDO_EN
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3.3
Setting GPSMODE0 to GPSMODE12
The start-up configuration of a ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. If Flash memory is available, configuration data can be stored in Flash memory. If EEPROM memory is connected, configuration data can be stored in EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 =0).
Table 3-3.
Pin GPSMODE0 GPSMODE1 GPSMODE2 GPSMODE3 GPSMODE4 GPSMODE5 GPSMODE6 GPSMODE7 GPSMODE8 GPSMODE9 GPSMODE10 GPSMODE11 GPSMODE12
GPSMODE Functions
Function Enable configuration with GPSMODE pins This pin is used for FixNow functionality and not used for GPSMODE configuration GPS sensitivity settings This pin (NAADET1) is used as active antenna supervisor input and not used for GPSMODE configuration Serial I/O configuration USB Power Mode General I/O Configuration This pin (NAADET0) is used as active antenna supervisor input and not used for GPSMODE configuration General I/O Configuration Serial I/O configuration
3.3.1
Enable GPSMODE Pin Configuration Table 3-4. Enable Configuration with GPSMODE Pins
GPSMODE0 (Reset = PD) Description 0 1 Ignore all GPSMODE pins. The default settings as indicated below are used Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to12]
3.3.2
Sensitivity Settings Table 3-5.
GPSMODE3 (Fixed PU) 0 0 1 1
GPS Sensitivity Settings
GPSMODE2 (Reset = PU) Description 0 1 0 1 Auto mode Fast mode Normal mode (Default) High sensitivity
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3.3.3 Serial I/O Configuration The ATR0621 features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port. In all configurations discussed below, all protocols are enabled on all ports. But output messages are enabled in a way that ports appear to communicate at only one protocol. However, each port will accept any input message in any of the three implemented protocols.
Table 3-6.
GPSMODE12 (Reset = PU) 0 0 0 0 1 1 1 1
Serial I/O Configuration
GPSMODE6 (Reset = PU) 0 0 1 1 0 0 1 1 USART1 USART2 GPSMODE5 (Output Protocol/ (Output Protocol/ (Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages Information Messages 0 1 0 1 0 1 0 1 UBX/57.6 UBX/38.4 UBX/19.2 -/Auto NMEA/19.2 NMEA/4.8 NMEA/9.6 UBX/115.2 NMEA/19.2 NMEA/9.6 NMEA/4.8 -/Auto UBX/57.6 UBX/19.2 UBX/38.4 NMEA/19.2 High Medium Low Off High Low Medium Debug User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error None User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error All
Both USART ports accept input messages in all three supported protocols (NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed. Response to a query input message will always use the same protocol as the query input message. In Auto Mode, no output message is sent out by default, but all input messages are accepted at any supported baud rate. Response to query input commands will be given the same protocol and baud rate as it was used for the query command. Using the respective configuration commands, periodic output messages can be enabled. The following message settings are used in Table 3-6:
Table 3-7.
NMEA Port UBX Port
Supported Messages at Setting Low
Standard NAV GGA, RMC SOL, SVINFO
Table 3-8.
NMEA Port UBX Port
Supported Messages at Setting Medium
Standard NAV GGA, RMC, GSA, GSV, GLL, VTG, ZDA SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK
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Table 3-9.
NMEA Port
Supported Messages at Setting High
Standard Proprietary NAV MON GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD, IO, IPC
UBX Port
Table 3-10.
Supported Messages at Setting Debug (Additional Undocumented Message May be Part of Output Data)
Standard Proprietary NAV GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD, IO, IPC RAW (RAW message support requires an additional license)
NMEA Port
UBX Port
MON RXM
The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM-Defaults):
Table 3-11.
Serial I/O Default Setting if GPSMODE Configuration is Deselected (GPSMODE0 = 0)
USART1/USB NMEA USART2 UBX 57.6, Auto enabled UBX, NMEA, RTCM UBX NAV: SOL, SVINFO User, Notice, Warning, Error
Baud Rate (kBaud) Input Protocol Output Protocol Messages Information Messages (UBX INF or NMEA TXT)
57.6, Auto enabled UBX, NMEA, RTCM NMEA GGA, RMC, GSA, GSV User, Notice, Warning, Error
3.3.4
USB Power Mode For correct response to the USB host queries, the device has to know its power mode. This is configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported to the USB host; that is, the device classifies itself as a "low-power bus-powered function" with no more than one USB power unit load.
Table 3-12.
0 1
USB Power Modes
USB device is bus-powered (max. current limit 100 mA) USB device is self-powered (Default)
GPSMODE7 (Reset = PU) Description
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3.3.5 Active Antenna Supervisor If GPSMODE configuration is enabled, the two pins P0/NANTSHORT and P15/ANTON, plus one pin of P25/NAADET0/MISO or P14/NAADET1 are initialized as general purpose I/Os and used as follows: * P15/ANTON is an output which can be used to switch on and off the antenna power supply. * Input P0/NANTSHORT will indicate an antenna short circuit, that is, zero DC voltage at the antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is assumed that also input P0/NANTSHORT will signal zero DC voltage, that is, switch to its active low state. * Input P25/NAADET0/MISO or P14/NAADET1 will indicate that a DC current is sunk into the antenna. In case of short circuit, both P0 and P25/P14 will be active, that is, at low level. If the antenna is switched off by output P15/ANTON, it is assumed that input P25/NAADET0/MISO will also signal zero DC current, that is, switch to its active low state. Which pin is used as NAADET (P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (Table 3-14). Table 3-13.
Pin P0/NANTSHORT P25/NAADET0/ MISO or P14/NAADET1 P15/ANTON
Pin Usage of Active Antenna Supervisor
Usage NANTSHORT Meaning Active antenna short circuit detection High = No antenna DC short circuit present Low = Antenna DC short circuit present Active antenna detection input High = No active antenna present Low = Active antenna is present Active antenna power on output High = Power supply to active antenna is switched on Low = Power supply to active antenna is switched off
NAADET
ANTON
Table 3-14.
Antenna Detection I/O Settings
Comment
GPSMODE11 GPSMODE10 GPSMODE9 (Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 P25/NAADET0/MISO P25/NAADET0/MISO P14/NAADET1 P14/NAADET1 (Default) P14/NAADET1 P14/NAADET1 P25/NAADET0/MISO P25/NAADET0/MISO
Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting.
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The Antenna Supervisor Software will be configured as follows: 1. Enable Control Signal 2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected via NANTSHORT) 3. Enable Open Circuit Detection via NAADET
3.4
External Connections for a Working GPS System
Example of an External Connection
SIGH SIGL SC P1 P2 NC See Table 3-15 NC SIGHI SIGLO CLK23 RF_ON NSLEEP NRESET EM_DA0 - 15 EM_A1 - 19
Figure 3-2.
ATR0601
ATR0621
P8 P20 USB_DM USB_DP P31 P18
STATUS LED TIMEPULSE Optional USB Optional USART 1 Optional USART 2 NC 32.368 kHz (see RTC)
See Table 3-15 See Table 3-15 See Table 3-15 See Table 3-15 See Table 3-15 NC NC NC NC NC NC NC GND +3V (see Power Supply)
P0 - 7 P9 - 15 P16 - 17 P19 P23 - 30 TMS TCK TDI NTRST TDO TEST_MODE DBG_EN GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18
P22 P21 TOUT1 XT_IN XT_OUT
+3V (see Power Supply)
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Table 3-15.
Pin Name P0/NANTSHORT
Recommended Pin Connection
Recommended External Circuit Internal pull-down resistor; can be left open. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if configured as output by user application. If this pin is left open, the GPSMODE pin configuration feature must be completely disabled by user application. Internal pull-down resistor, leave open. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Pull-up resistor to VDD18 or pull-down resistor to GND or connect to GND or VDD18 if unused. Never leave open. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Pull-up resistor to VDD18 or pull-down resistor to GND (this pin is used as address line EM_A21 by standard firmware, do not connect to GND or VDD18 directly). Never leave open. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application, or connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application, or connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 10. Never leave open. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Internal pull-down resistor; can be left open. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application.
P1/GPSMODE0
P2/BOOT_MODE P3/NCS1 P4/NCS0 P5/NWE/NWR0 P6/NOE/NRD P7/NUB/NWR1 P8/STATUSLED P9/EXTINT0 P10/EM_A0/NLB P11/EM_A21
P12/NCS2/GPSMODE2
P13/EXTINT1/GPSMODE3/ NCS3
P14/SCK0/GPSMODE4
P15/ANTON P16/NWD_OVF
P17/SCK1/GPSMODE5
P18/TXD1 Note:
Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. "Never leave open" means: This pin needs a defined level, even if VDD18 is not supplied and system is in backup mode.
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4890AS-GPS-09/05
Table 3-15.
Pin Name
Recommended Pin Connection (Continued)
Recommended External Circuit Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Pull-up resistor to VDD18 or connect to VDD18 if unused. Pull-down resistor also possible if used as GPIO input by user application. Never leave open. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Use pull-up resistor to VDD18, if SPI is used. Never leave open. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Output in default ROM firmware: leave open; only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and not always driven from external sources. Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user application; connect to GND or VDD18 if unused or used as GPSMODE pin only. See GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 10. Can be left open if not used as GPSMODE pin and configured as output by user application. Internal pull-up resistor, leave open. Pull-up resistor to VDD18 or connect to VDD18 if unused. Pull-down resistor also possible if used as GPIO input by user application. Never leave open.
P19/SIGLO2/GPSMODE6
P20/SCK2/TIMEPULSE P21/TXD2 P22/RXD2
P23/SCK/GPSMODE7
P24/MOSI/GPSMODE8
P25/MISO/GPSMODE9
P26/NSS/NPCS0/ GPSMODE10
P27/NPCS1/GPSMODE11
P28/EM_A20/NPCS2
P29/NPCS3/GPSMODE12
P30/AGCOUT0 P31/RXD1 EM_DA0 to EM_DA15 Note:
If no external memory is used, can be left open (internal pull-down). If an external memory is connected to these pins, a defined level is needed when all external memories are inactive. "Never leave open" means: This pin needs a defined level, even if VDD18 is not supplied and system is in backup mode.
16
ATR0621 [Preliminary]
4890AS-GPS-09/05
ATR0621 [Preliminary]
4. Oscillator
Figure 4-1. Crystal Connection
ATR0621 internal
XT_IN 32 kHz Crystal Oscillator 32.768 kHz 50 ppm XT_OUT
32.768 kHz clock
RTC
max. 25 pF
max. 25 pF
5. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Operating Free Air Temperature Range Storage Temperature DC Supply Voltage DC Supply Voltage DC Supply Voltage DC Supply Voltage DC Supply Voltage DC Supply Voltage VDD18 VDDIO VDD_USB LDO_IN LDOBAT_IN VBAT EM_DA0 to EM_DA15, P0, P3 to P7, P10, P11, P15, P28, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP Pin Symbol Min. -40 -60 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max. +85 +150 +1.95 +1.95 +3.6 +3.6 +3.6 +3.6 Unit C C V V V V V V
DC Input Voltage
-0.3
+1.95
V
DC Input Voltage DC Input Voltage Note:
-0.3
+3.6 +5.0
V V
P1, P2, P8, P9, P12 to P14, -0.3 P16 to P27, P29, P30 Minimum/maximum limits are at +25C ambient temperature, unless otherwise specified
17
4890AS-GPS-09/05
6. Power Consumption
Mode Sleep Shutdown Normal Note: Conditions At 1.8V, no CLK23 RTC and backup SRAM only Satellite acquisition Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA All channels disabled 1. Specified value only Typ. 0.065 25 14 11
(1)
Unit mA mA mA mA mA
0.007(1)
7. Electrical Characteristics
No. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 Parameters DC Supply Voltage Core DC Supply Voltage VDDIO Domain(1) DC Supply Voltage USB(2) DC Supply Voltage Backup Domain(3) DC Output Voltage VDD18 DC Output Voltage VDDIO Low-level Input Voltage VDD18 Domain High-level Input Voltage VDD18 Domain Low-level Input Voltage VDDIO Domain High-level Input Voltage VDDIO Domain Low-level Input Voltage VBAT18 Domain High-level Input Voltage VBAT18 Domain Low-level Input Voltage USB High-level Input Voltage USB VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDDIO = 1.65V to 3.6V VDDIO = 1.65V to 3.6V VBAT18 = 1.65V to 1.95V VBAT18 = 1.65V to 1.95V VDD_USB = 3.0V to 3.6V VDD_USB = 3.0V to 3.6V P9, P13, P22, P31 P9, P13, P22, P31 DP, DM DP, DM Test Conditions Pin VDD18 VDDIO VDD_USB VBAT18 Symbol VDD18 VDDIO VDDUSB VBAT18 VO,18 VO,IO VIL,18 VIH,18 VIL,IO VIH,IO VIL,BAT VIH,BAT VIL,USB VIH,USB Min. 1.65 1.65 3.0 1.65 0 0 -0.3 0.7 x VDD18 -0.3 0.7 x VDDIO -0.3 1.46 -0.3 2.0 Typ. 1.8 1.8/3.3 3.3 1.8 Max. 1.95 3.6 3.6 1.95 VDD18 VDDIO 0.3 x VDD18 VDD18 + 0.3 0.3 x VDDIO 5.0 0.41 5.0 0.8 VDD_USB + 0.3 Unit V V V V V V V V V V V V V V Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to 1.8V or 0V supply. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
18
ATR0621 [Preliminary]
4890AS-GPS-09/05
ATR0621 [Preliminary]
8. Ordering Information
Extended Type Number ATR0621-7FQY Package LFBGA100 Remarks 9 mm x 9 mm, 0.80 mm pitch, Pb-free
9. Package LFBGA100
Package: R-LFGBA 100_G Dimensions in mm 0.08 M 0.15 M A1 Corner Top View 12345 A B C D E F G H J K 6 7 8 9 10 Bottom View 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K A1 Corner
C BA
0.38 ... 0.48 (100x)
90.05
7.2
0.8
0.8 A 7.2
technical drawings according to DIN specifications
0.15 (4x) C B 90.05 0.53 ref. C (0.36)
0.12 C
0.2 C
0.27 ... 0.37
1.4 max
Seating plane
Drawing-No.: 6.580-5003.01-4 Issue: 1; 02.09.05
19
4890AS-GPS-09/05
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4890AS-GPS-09/05

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